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Simplified cross-sectional illustration of the process of fabrication of a CMOS inverter on p-type substrate in semiconductor microfabrication. Each etch step is detailed in the following image as a cut-through of a single transistor device. Note: Gate, source and drain contacts are not normally in the same plane in real devices, and the diagram is not to scale.
Wafer fabrication is a procedure composed of many repeated sequential processes to produce complete electrical or photonic circuits on semiconductor wafers in semiconductor device fabrication process. Examples include production of radio frequency (RF) amplifiers, LEDs, optical computer components, and microprocessors for computers. Wafer fabrication is used to build components with the necessary electrical structures.
The main process begins with electrical engineers designing the circuit and defining its functions, and specifying the signals, inputs/outputs and voltages needed. These electrical circuit specifications are entered into electrical circuit design software, such as SPICE, and then imported into circuit layout programs, which are similar to ones used for computer aided design. This is necessary for the layers to be defined for photomask production. The resolution of the circuits increases rapidly with each step in design, as the scale of the circuits at the start of the design process is already being measured in fractions of micrometers. Each step thus increases circuit density for a given area.
The silicon wafers start out blank and pure. The circuits are built in layers in clean rooms. First, photoresist patterns are photo-masked in micrometer detail onto the wafers' surface. The wafers are then exposed to short-wave ultraviolet light and the unexposed areas are thus etched away and cleaned. Hot chemical vapors are deposited on to the desired zones and baked in high heat, which permeate the vapors into the desired zones. In some cases, ions, such as O2+ or O+, are implanted in precise patterns and at a specific depth by using RF-driven ion sources.
These steps are often repeated many hundreds of times, depending on the complexity of the desired circuit and its connections.
New processes to accomplish each of these steps with better resolution and in improved ways emerge every year, with the result of constantly changing technology in the wafer fabrication industry. New technologies result in denser packing of minuscule surface features such as transistors and micro-electro-mechanical systems (MEMS). This increased density continues the trend often cited as Moore's Law.
A fab is a common term for where these processes are accomplished. Often the fab is owned by the company that sells the chips, such as Intel, Texas Instruments, or Freescale. A foundry is a fab at which semiconductor chips or wafers are fabricated to order for third party companies that sell the chip, such as fabs owned by Taiwan Semiconductor Manufacturing Company (TSMC), United Microelectronics Corporation (UMC), GlobalFoundries and Semiconductor Manufacturing International Corporation (SMIC).
In the cost of building the next generation wafer fab was over $10 billion.[1]
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Referred to respectively as the wafer fab equipment [2] or wafer front end [3] (equipment) market, both using the acronym WFE, the market is that of the manufacturers of the machines which in turn manufacture semiconductors. The apexresearch link in identified Applied Materials, ASML, KLA-Tencor, Lam Research, and Dainippon Screen Manufacturing as market participants[2] while the electronicsweekly.com report, citing The Information Network's president Robert Castellano, focused on the respective market shares commanded by the two leaders, Applied Materials and ASML.[3]
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Semiconductor chips have high technical requirements and high prices for sputtered targets. Their requirements for sputtered targets' purity and technology are higher than flat-panel displays, solar cells, and other applications. Semiconductor chips set extremely strict standards for the purity of sputtering target metal materials, internal microstructure, and other aspects. If the impurity content of the sputtering target is too high, the film formed can't meet the required electrical performance. In the sputtering process, it is easy to form particles on the wafer, resulting in a short circuit or damage of the circuit, which seriously affect the performance of the film. Generally speaking, chip manufacturing requires the highest purity of sputtering target metal, which is usually 99.% (5N5) or more, while flat-panel display and solar cell require 99.999% (5N) or 99.995% (4N5) or more, respectively.
Semiconductor sputtering target application
The sputtering target is used for the fabrication of the barrier layer and the packaging metal wiring layer. In the wafer manufacturing process, the target material is mainly used to make the wafer conductive layer, barrier layer, and metal grid. In the chip packaging process, the sputtering target material is used to generate the metal layer under the bump, wiring layer, and other metal materials. Although the amount of target materials used in wafer manufacturing and chip packaging is small, according to SEMI statistics, the cost of target materials in wafer manufacturing and packaging process accounts for about 3%. However, the quality of sputtering target materials directly affects the uniformity and performance of conductive layer and barrier layer, and further affects chip transmission speed and stability, so sputtering target materials are the core raw materials for semiconductor production one of the materials.
Sputtering target for semiconductor
In the process of wafer fabrication, sputtering targets for semiconductors are mainly used for the fabrication of the conductive layer, the barrier layer, and metal grid, which are mainly used for aluminum, titanium, copper, tantalum, and other metals. AEM Deposition, as a professional sputtering target manufacturer, provides pure metal sputtering targets suitable for semiconductors. See the table below:
The metal target materials for chip packaging are similar to wafer fabrication, including copper, aluminum, and titanium. Among them, the main metal targets used in the fabrication of the conducting layer are aluminum sputtering target and copper sputtering target. The main metal targets used in the barrier layer are tantalum sputtering target and titanium sputtering target. The barrier layer has two main functions: one is to block and insulate to prevent the conductive layer metal from diffusing into the main material silicon of the wafer. The other is used as an adhesion for bonding metal silicon materials. Aluminum and titanium are used as thin-film materials for conductor and barrier layer for wafers above 110 nm technology node, copper and tantalum are used as thin-film materials for conductor and barrier layer for wafers below 110 nm technology node. With the reduction of the wafer manufacturing process, the proportion of copper target, tantalum target, and titanium target for metal grid continue to increase in the future.
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